The present invention relates to a semiconductor design technology, and more particularly, to a data output circuit for outputting internal information data such as a vendor ID through an input/output pad.
A double data rate synchronous dynamic random access memory (DDR SDRAM) employs the specification of SDRAM that exchanges data not only at a rising edge but also at a falling edge of a clock. Therefore, the DDR SDRAM operates at a higher speed than that of a single data rate (SDR) SDRAM that exchanges data with an external device only at a rising edge of a clock. However, there is a limitation to increase an operation speed of an internal circuit of SDRAM. In order to overcome such a limitation, a prefetch method was introduced. In the prefetch method, N-bit input/output data is prefetched and stored at each input/output pin DQ. Then, the stored N-bit input/output data is loaded at each rising/falling edge of a clock when data is inputted or outputted.
Such a prefetch method includes not only a 2-bit prefetch method for prefetching and storing two-bits per each input/output pin DQ but also 4-bit and 8-bit prefetch methods for prefetching and storing 4-bit or 8-bit data per each input/output pin DQ. The DDR2 SDRAM employs the 4-bit prefetch method for inputting and outputting 4-bit data during two clock cycles, that is, rising/falling edges of four consecutive clocks. A DDR3 SDRAM employs the 8-bit prefetch method for inputting and outputting 8-bit data during four clock cycles, that is, rising/falling edges of 8 consecutive clocks.
Since the prefetch method must latch a plurality of data at the same time, more internal data transmission lines are required. Therefore, a 8-bit prefetch type SDRAM includes internal data transmission lines two times more than that in a 4-bit prefetch type SDRAM. However, data must be processed with an enough margin in the SDRAM because the clock cycle required for inputting and outputting corresponding prefetched data increases as the number of transmission lines increases. Therefore, the prefetched data is divided based on a time division method and transmitted in order to reduce the number of data transmission lines.
FIGS. 1 and 2 are diagrams illustrating a typical data transmitting and receiving circuit of a semiconductor memory device for describing a write operation and a read operation. FIGS. 1 and 2 show data transmission after 2N-bit parallel data is divided into N-bits of parallel data based on a time division scheme.
FIG. 1 is a diagram for describing a write operation of a semiconductor memory device. As shown in FIG. 1, the data transmitting and receiving circuit includes a first latch 101, an output driver 103, a parallel data line unit 105, and a clock counter 107.
Data serially inputted from an external device to a semiconductor memory device is prefetched by 2N-bit in a pipe latch (not shown) of an input/output interface. The pipe latch transmits the 2N-bits prefetched parallel data to a first line DIO<1:2N> in response to a predetermined strobe signal.
The clock counter 107 generates a first delayed control signal STDD_1 by delaying a first control signal ST_1 obtained from the predetermined strobe signal. The first control signal ST_1 and the first delayed control signal STDD_1 are signals for deciding transmitting and receiving timing of the output driver and the first latch 101. The clock counter 107 counts a clock cycle CLK and delays the first control signal ST_1 as much as a predetermined clock cycle. For example, if the semiconductor memory device employs a 8-bit prefetch method, a first delayed control signal STDD_1 is enabled when two clock cycles CLK passes after the first control signal ST_1 is enabled.
The output driver 103 receives 2N-bit prefetched parallel data, divides the parallel data based on a time division scheme in response to the first control signal ST_1 and the first delayed control signal STDD_1, and outputs N-bit parallel data. Therefore, the parallel data line unit 105 may include as N transmission lines GIO<1:N> instead of 2N transmission lines. The parallel data line unit 105 transmits data in bi-direction in a write operation and a read operation.
The first latch 101 latches N-bit parallel data which is divided based on a time division scheme and transmitted in response to a first control signal ST_1 and a first delayed control signal STDD_1 and sorts the latched data as 2N-bit parallel data. When a write driver (not shown) is enabled, the 2N-bit parallel data is transmitted to the second line LIO<1:2N> and stored in a memory cell. Sorting, in general, may include, but is not limited to, dividing parallel data into one or more groups of divided parallel data, or combining one or more groups of divided parallel data into parallel data.
FIG. 2 is a diagram for describing a read operation of a semiconductor memory device. As shown, a data transmitting/receiving circuit includes an input/output sense amp 201, a second latch 203, a parallel data line unit 105, and a delay unit 207.
If a column is selected by a predetermined column selection signal, 2N-bit parallel data is transmitted from the memory cell to the second line LIO<1:2N> and inputted to the input/output sense amp 201.
The delay unit 203 generates a second delayed control signal STDD_2 by delaying a second control signal ST_2 obtained from the predetermined column selection signal. The second control signal ST_2 and the second delayed control signal STDD_2 decide transmitting and receiving timings of the input/output sense amp 201 and the second latch 203. The 2N-bit parallel data and the clock CLK are transferred through different paths. Therefore, it is difficult to delay the second control signal ST_2 as much as a predetermined delay amount using the clock counter 107 used in a write operation because the delay amounts of the 2N-bit parallel data and the clock CLK vary according to a corresponding path. Therefore, if the semiconductor memory device employs the 8-bit prefetch method, the second control signal ST_2 is delayed by the delay unit 203 that has a predetermined delay amount as much as two clock cycles CLK based on the highest operation frequency of a semiconductor memory device in a write operation and a read operation.
The input/output sense amp 201 receives 2N-bit parallel data, divide the receive 2N-bit parallel data based on a time division scheme in response to the second control signal ST_2 and the second delayed control signal STDD_2 and outputs N-bit parallel data. Therefore, the parallel data line unit 105 may include N transmission lines GIO<1:N> instead of 2N transmission lines.
The second latch 203 latches N-bit parallel data in response to the second control signal ST_2 and the second delayed control signal STDD_2, sorts the latched N-bit parallel data to 2N-bit parallel data, and outputs the 2N-bit parallel data to an input/output interface (not shown).
FIG. 3 is a timing diagram for describing a write operation and a read operation of a data transmitting and receiving circuit of FIGS. 1 and 2. That is, FIG. 3 shows a timing diagram for a write operation and a read operation of a data transmitting and receiving circuit employing a 8-bit prefetch method at radio frequency where N=4.
In case of a write operation, an output driver 103 divides 8-bit prefetched data D1 to D8 based on a time division scheme, and transmits 4-bit data D1, D2, D3, and D4 among the 8-bit perfected data D1 to D8 through four transmission lines GIO<1:4> of a parallel data line unit 105 in response to the first control signal ST_1. After two clock cycles CLK, the output driver 103 transmits remaining 4-bit data D5, D6, D7, and D8 through four transmission lines GIO<1:4> of the parallel data line unit 105 in response to the first delayed control signal STDD_1 which is enabled by the clock counter 107.
In case of a read operation, the input/output sense amp 201 divides 8-bit parallel data D1 to D8 outputted from a memory cell based on a time division scheme, and transmits 4-bit data D1 to D4 among 8-bit parallel data D1 to D8 in response to the second control signal ST_2 through four transmission lines GIO<1:4> of the parallel data line unit 105. After two cycles of a clock CLK, the input/output sense amp 201 transmits remaining 4-bit data D5, D6, D7, and D8 in response to the second delayed control signal STDD_2 enabled by the delay unit 203 through four transmission lines GIO<1:4> of the parallel data line unit 105.
FIG. 4 is a timing diagram for describing a write operation and a read operation of a data transmitting and receiving circuit of FIGS. 1 and 2, which employs a 8-bit prefetch method at a low frequency where N=4.
In case of a write operation, a margin of time-divided and transmitted data is uniform because the clock counter counts a clock cycle CLK and the first delayed control signal STDD 1 is enabled.
In case of a read operation, however, a margin of time-divided and transmitted data is not uniform when a delay amount of the delay unit 203 is adjusted to two clock cycles of a high frequency of FIG. 3. That is, in case of a data transmitting circuit according to the related art, margins of the parallel data D1 to D4 transmitted in response to the second control signal ST_2 are reduced compared to margins of parallel data D5 to D8 transmitted in response to the second delayed control signal STDD_2. Therefore, an error may occur in transmitting data.
Also, the data transmission circuit according to the related art has a problem of high power consumption because the clock counter 107 always counts the clocks CLK in regardless of the operations of the output driver 103.